SRAMs are one of the most popular ways to store data in electronic systems. Similarly, embedded SRAMs are a vital building block in integrated circuits. SRAMs are a preferred method of implementing embedded memories owing to higher speed, robust design, and ease of integration. SRAMs, in general, occupy a significantly large portion of the chip's die area, making it an important block in terms of area, yield, reliability and power consumption. With increasing demand for highly integrated System on Chip (SoC), improving various aspects of embedded SRAMs have received a significant interest.
The six transistor SRAM cell is the most popular configuration because of its high speed and robustness. However the 6T SRAM cell, shown in FIG. 1, suffers from a relatively high vulnerability to soft errors. At the heart of the 6T SRAM cell is the four transistor dual-inverter storage cell shown in FIG. 2. The inherent feedback of the back-to-back inverters means that if sufficient charge is collected on one node, the feedback will cause the second node to also switch. This results in an erroneous state being stored, and the cell cannot recover.
Flip-flops are critical components in integrated circuits. Hip-flops enable sequential logic by storing the result of combinational logic. A flip-flop stores data by sampling the input data signal with a clock signal at a particular instant of time, typically at the edge of the clock. Thus, the output of the flip-flop is sensitive to the input data signal only at the clock edge. At all other times, the flip-flop's output is constant and does not respond to changes in input data signal.
A flip-flop can be realized in a variety of ways. A typical way of realizing a flip-flop is to use two series connected latches called master and slave. This architecture of flip-flop is called the master-slave D-flip-flop (DFF), a schematic of which is given in FIG. 3. Whatever the architecture every flip-flop must have a storage element. Most static flip-flops use a dual-inverter structure, shown in FIG. 2.
The scaling of CMOS processes has resulted in lower node capacitance and lower supply voltages in integrated circuits. The result of these effects is that less charge is used to store data in a storage cell. The increased density enabled by the smaller geometries of scaled processes has also enabled the integration of large SRAM arrays and large numbers of flip-flops. These conditions resulted in an increased sensitivity to transients induced by ionizing radiation consisting of energetic cosmic neutrons and alpha particles. When these particles strike the chip they generate a large number of electron hole pairs. Depending on the location of the particle strike the deposited charge may be collected by a node in a storage cell. If sufficient charge is collected the storage cell can switch its logical state, which is called a soft error. In view of this vulnerability numerous methods have been proposed to improve the robustness of the storage cell. More effort has been put into improving the soft-error robustness of SRAM cells, however the SER of flip-flops has been continually degrading to the point where is has become a significant reliability consideration. Both the 6T SRAM and the master-slave static CMOS DFF use the dual-inverter storage cell to hold a logical state. For both circuits the data value stored in this structure can be susceptible to soft errors. If a soft error transient is able to change the state of one node, the feedback of the dual-inverter storage cell will change the second node and result in erroneous data being stored.
FIG. 4 shows the schematic diagram of an SRAM cell which has an improved robustness to radiation induced soft errors. In the proposed circuit the SRAM cell has the same dual-inverter storage cell as in the traditional case, however it also includes a coupling capacitor between the two nodes where the data is stored. The effect of adding the coupling capacitor is that the critical charge (Qc) of the cell is significantly increased. The critical charge is the minimum amount of charge which will result in a soft error. However, the addition of a large, area efficient coupling capacitor requires a special semiconductor manufacturing process. Therefore this SRAM cell is not easily integrated into common Complementary Metal-Oxide-Semiconductor (CMOS) processes. As a result, for Application Specific Integrated Circuits (ASICs) where embedded SRAM cells are widely realized using standard CMOS process, this approach is costly to implement. Another problem with this approach is that while the capacitor increases the critical charge, it also makes the cell slower to write to. For data to be written into this SRAM cell the coupling capacitor will have to be charged/discharged, which will take more time than for a standard 6T SRAM cell. This results in a lower frequency of operation, which is again not desirable. Another drawback of this cell is that the extra capacitance which must be charged and discharged results in larger power consumption compared to the standard 6T SRAM cell.
FIG. 5 shows the schematic diagram of a storage cell which has four extra transistors in order to improve its robustness to soft errors. This circuit is known as the DICE cell, which stands for dual-interlocking storage cell. In the proposed solution, the data is stored on multiple nodes and the storage cell is immune to single node upsets. However, the SRAM cell based on the DICE storage cell requires twice as many transistors to implement compared with the standard 6T SRAM circuit, making it expensive. Also, in order for this cell to be used in a flip-flop, at least three nodes must be accessed. The result is that flip-flops which implement this storage cell require a greater number of transistors and use more power.
FIG. 6 shows the schematic diagram of a third storage cell which has an improved robustness to soft errors. This circuit consists of eight transistors and is similar to the DICE cell in that data is stored at multiple nodes. However, in this storage cell data is stored on four nodes which are interconnected using four half-latches. This SRAM cell is almost completely immune to soft-error induced upsets. The SRAM circuit based on this storage cell requires only ten transistors, which is more than the 6T SRAM cell, but less than the DICE SRAM cell. This storage cell can also be used to implement flip-flops. This data on this storage cell can be changed by accessing only two nodes, and as such fewer transistors are required as compared to the DICE based flip-flop.